Modern computer systems use dynamic memory chips that are arranged as a matrix of rows and columns. FIGS. 1–3 illustrate examples of such dynamic memory chips. FIG. 1 shows various memory cells disbursed within different banks 1–8. FIG. 2 illustrates certain of the components within a given bank of memory. Associated with the bank is a row decoder 22, a column decoder 24, a memory array 26, a sense amplifier 28 and column selection circuitry 30, also referred to herein circuitry 110.
A portion of the memory array 26 is further illustrated in FIG. 3 with a plurality of memory cells 30 attached to particular rows 32, (e.g., word lines) and columns 34 (e.g., bitlines).
Operation of memories as described above typically involves an address input to the memory array, with a memory cell associated with the input address being accessed and the data stored in that memory cell being read out. Similarly, if data needs to be written into the memory array, the data will have an associated address, and that address will be used to store the data into the memory cell associated with that particular address.
Memory chips as described above also use techniques in order to increase their speed and efficiency. Using conventional techniques, such chips can access a word of data in a different column of a pre-selected row in a very efficient manner (typically one word per cycle) but access to a word in a different (non-selected) row is relatively slow (typically ten cycles). Furthermore, since these chips are divided into banks as mentioned previously, which each include separate row/column matrices, as illustrated in FIG. 3, this allows for a row access to be performed on one bank while column accesses are being made to a different bank. While such operation improves efficiency somewhat, improvements are still needed.
Particularly, conventional memory systems process memory operations in the order they are received. If the memory system receives addresses in the same row as the previous address, it performs a column access. If an address in the same row as the previous address is not received, the memory system performs a row access. While this mode of operation yields adequate performance for access patterns with significant spatial locality, performance is degraded by almost 90% for unstructured address streams. Such unstructured address streams are typically of indirect vector or stream references.
These and other challenges to memory system operation and access have hindered certain aspects of memory and memory-related functions.